Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and Flash memory, wherein the ROM and the Flash memory are also resided in non-volatile memory.
For a conventional Flash memory device, a plurality of one-transistor core cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally with the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions. One type of architecture used for Flash memories is typically referred to as a NOR Flash memory architecture which is an array of Flash EEPROM cells which are divided into a plurality of sectors. Further, the memory cells within each sector are arranged in rows of wordlines and columns of bit lines intersecting the rows of wordlines. To sum up, a typical flash memory comprises a memory array, which includes a large number of memory cells divided in sectors. The flash memory is differentiated from other non-volatile memory in that flash memory cells can be erased and reprogrammed in blocks instead of one byte at a time.
Furthermore, for the cells in the Flash memory, each of the flash memory cells is connected with a row or X-decoder but a column or Y-decoder is shared by multiple memory cells. An example of a typical memory cell architecture is illustrated in FIG. 1, which is a diagram illustrating an conventional architecture of a plurality of memory cells corresponded with a plurality of decoders for a semiconductor memory. This architecture uses an X-decoder for each cell of memory. FIG. 1 shows two columns of memory cells. Each column is comprised of eight flash memory array cells 100-115. Each memory array cell 100-115 has a dedicated X-decoder 1101-1115 respectively, and each column of cells is shared a Y-decoder 131-132 respectively.
In order for memory manufacturers to remain competitive, memory designers must constantly increase the density, shrank the entire size, reduce the power consumption and enhance read speed of flash memory devices. In particular, there has arisen a need to provide a way of reducing the power consumption or the capacitive loading in Flash memory X-decoder in order to produce accurate voltage control at selected wordlines.
For the requirements stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory decoding architecture that reduces power consumption for reading operation in a semiconductor memory. Hence a novel power saving method and decoder for a semiconductor memory is thus provided.